Dr. Ramon Canal

Contact Information

Address

.Campus Nord UPC C6-107, Cr. Jordi Girona, 1-3, 08034 Barcelona

Email

.rcanal@ac.upc.edu

Phone

.+34 934054034

Web page

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Ramon Canal

Short bio

Ramon Canal received his M.S. (1998) and Ph.D. (2004) degrees from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, EU. He joined the faculty of the Computer Architecture Department of UPC in 2003. He was an Erasmus Student at the University of Bath (UK) in 1998, he worked at Sun Microsystems in 2000, and he was a Fulbright visiting scholar at Harvard University in 2006/2007 and a visiting professor at the University of Cyprus in 2019/2020. His research focuses on power and thermal aware architectures, as well as reliability and security. He has an extensive list of publications and several invited talks attracting over 2000 references (Google Scholar). He has been program committee member in several editions of HPCA, ISCA, MICRO, DATE, HiPC, IPDPS, ICCD, ICPADS, CF. He has been co-general chair of HPCA 2016 and IOLTS 2012. He has been track co-chair for DATE 2019 and 2020. He has been financial co-chair of ETS 2022. He is currently an associate editor of the ACM Transactions on Architecture and Code Optimization (TACO) and the Journal of Parallel and Distributed Computing (JPDC).

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Publications

Journals

Papers

  1. “Malicious website detection through Deep Learning algorithms” N. Gutierrez, B. Otero, E. Rodriguez, and R. Canal 7th International Conference on Machine Learning, Optimization, and Data Science (LOD), Grasmere, Lake District, England, October 2021, LNCS xxxx.
  2. “Privacy preserving Deep Learning framework in Fog computing“
    N. Gutierrez, E. Rodriguez, S. Mus, B. Otero and R. Canal 6th International Conference on Machine Learning, Optimization, and Data Science (LOD), Siena, Italy, 2020, LNCS 12565.
  3. “ Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis” A. Lasheras, R. Canal, E. Rodríguez, L. Cassano
  4. 2020 IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Naples, Italy, 2020, pp. 1-6.
  5. “Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking” A. Lasheras, R. Canal, E. Rodríguez, L. Cassano 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Noordwijk, Netherlands, 2019, pp. 1-6
  6. “SafeX: Open Source Hardware and Software Components for Safety-Critical Systems“
    S. Alcaide, G. Cabo, F. Bas, P. Benedicte, F. Fuentes, F. Chang, I. Lasfar, R. Canal, J. Abella
    2022 IEEE Forum on specification and Design Languages Sept. 2022.
  7. “SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications “
    R. Canal, F. Bas, S. Alcaide, G. Cabo, P. Benedicte, F. Fuentes, F. Chang, I. Lasfar, J. Abella
    2022 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) July 2022.
  8. “SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays “
    R. Canal, Y. Sazeides, A. Bramnik,
    2021 IEEE Design, Automation and Test in Europe Conference (DATE) February 2021.
  9. “2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)“
    Y. Sazeides, A. Bramnik, R. Gabor, C. Nicopoulos, R. Canal, D. Konstantinou, G. Dimitrakopoulos
    2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) October 2020.
  10. “Challenges in Deeply Heterogeneous High Performance Systems“
    G.Agosta, W. Fornaciari, A. Cilardo, J.Flich, C. Hernandez, M. Kulczewski, G. Massari, R. Tornero, M. Zapater, D. Atienza and R. Canal
    2019 EUROMICRO Digital System Design Conference, Kallithea (Greece), August 2019.
  11. “Modern Gain-Cell Memories in Advanced Technologies“
    E. Amat, R. Canal, A. Rubio
    24th IEEE International On-Line Testing Symposium (IOLTS’18), Platja d’Aro (Catalonia), July 2018
  12. “Review on new eDRAM configurations for next nano-metric electronics era“
    E. Amat, A. Calomarde, R. Canal, A. Rubio
    8th International Conference on Materials Engineering for Resources (ICMR2017),  Akita (Japan), October 2017
  13. “Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level“
    E. Amat, A. Calomarde, R. Canal, A. Rubio
    27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS),  Thessaloniki (Greece), September 2017
  14. “MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment“
    M. Kaliorakis, D. Gizopoulos, R. Canal, A. Gonzalez
    IEEE/ACM International Symposium on Computer Architecture (ISCA-44),  Toronto (Canada), June 2017
  15. “Cross-Layer System Reliability Assessment Against Hardware Faults“
    A. Vallero, A. Savino, G. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio, G. Di Natale
    IEEE International Test Conference (ITC-47),  Fort Worth (TX, USA), November 2016
  16. “SRAM Memory Margin Probability Failure Estimation using Gaussian Process Regression “M. Rana, R. Canal, J. Han and B. Cockburn
    IEEE International Conference on Computer Design   (ICCD-34),  Phoenix (AZ, USA), October 2016
  17. “MASkIt: Soft Error Rate Estimation for Combinational Circuits“M. Anglada, R. Canal, J. L. Aragón and A. González
    IEEE International Conference on Computer Design   (ICCD-34),  Phoenix (AZ, USA), October 2016
  18. “Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation“M.Rana, R.Canal, E.Amat, A.Rubio
    22th IEEE International On-Line Testing Symposium (IOLTS’16), St. Feliu de Guíxols (Catalonia), July 2016
  19. “A Detailed Methodology to Compute Soft-Error Rates in Advanced Technologies“
    M. Riera, R. Canal, J. Abella. A. Gonzalez
    IEEE Design, Automation and Test in Europe Conference (DATE’16),  Dresden (Germany), March 2016
  20. “Early Component-Based System Reliability Analysis for Approximate Computing Systems“A. Vallero, A. Savino, G. Michele, M. Politano, S. Di Carlo, A. Chatzidimitriou, S. Tselonis, M. Kaliorakis, D. Gizopoulos, M. Riera, R. Canal, A. Gonzalez, M. Kooli, A. Bosio and G. Di Natale.
    2nd Workshop on Approximate Computing (WAPCO) (together with Hipeac Conference), Prague (Czech Republic), January 2016
  21. “Variability – Aware Design Space Exploration Of Embedded Memories“
    S. Ganapathy, G. Karakonstantis, A. Burg and R. Canal
    IEEE 28th Convention of Electrical and Electronics Engineers in Israel, Eilat (Israel), December 2014
  22. “REEM: Failure/Non-Failure region Estimation  method for SRAM yield analysis“
    M. Rana, R. Canal
    IEEE International Conference on Computer Design   (ICCD-32),  Seoul (Korea), October 2014
  23. “iRMW: A Low-Cost Technique to Reduce NBTI-Dependent Parametric Failures in L1 Caches”  (Best paper nomenee)
    S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio 
    IEEE International Conference on Computer Design   (ICCD-32),  Seoul (Korea), October 2014
  24. “Variability impact on on-chip memory data paths“
    E. Amat, A. Calomarde, R. Canal, A. Rubio
    IEEE 5th European Workshop on CMOS Variability (VARI’14),  Palma de Mallorca (Spain), September-October 2014
  25. “Cross-layer early reliability evaluation: Challenges and promises” (invited paper)
    S. Di Carlo, A. Vallero, D. Gizopoulos, G. Di Natale, A. Gonzalez, R. Canal, R. Mariani, M. Pipponzi, A. Grasset, P. Bonnot, F. Reichenbach, G. Rafiq, T. Loekstad
    20th IEEE International On-Line Testing Symposium (IOLTS’14), Platja d’Aro (Catalonia), July 2014
  26. “SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis“
    M. Rana, R. Canal
    IEEE Design, Automation and Test in Europe Conference (DATE’14),  Dresden (Germany), March 2014
  27. “DRAM-based Coherent Caches and how to take advantage of the coherence protocol to reduce the refresh power“
    Z. Jakšić, R. Canal
    IEEE Design, Automation and Test in Europe Conference (DATE’14),  Dresden (Germany), March 2014
  28. “INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis
    S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez and A. Rubio
    IEEE Design, Automation and Test in Europe Conference (DATE’14),  Dresden (Germany), March 2014
  29. “FinFET and III-V/Ge technology impact on 3T1D cell behavior”  (slides)
    E. Amat, A. Calomarde, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
    Intel Ireland Research Conference (IIRC), Dublin (Ireland), November 2013.
  30. “Variability Robustness Enhancement for 7nm FinFET 3T1D-DRAM Cells “
    E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
    IEEE 55th International Midwest Symposium on Circuits and systems (MWSCAS 2013) Columbus (Ohio, USA), August 2013
  31. “An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU“
    N. Jing, Y. Shen, Y. Lu, S. Ganapathy, Z. Mao, M. Guo, R. Canal, X. Liang
    ACM/IEEE 40th International Conference on Computer Architecture (ISCA’13), Tel-Aviv (Israel), June 2013
  32. “Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes“
    V. Lorente, A. Valero, J. Sahuquillo, S. Petit, R. Canal, P. Lopez, J. Duato
    IEEE Design, Automation and Test in Europe Conference (DATE’13),  Grenoble (France), March 2013
  33. “On the Effectiveness of Hybrid Recovery Techniques on Parametric Failures“
    S. Ganapathy, R. Canal,  A. Gonzalez, A. Rubio
    30th IEEE International Symposium on Quality Electronic Design (ISQED’13), Santa Clara (California, USA), March 2013
  34. “Effects of FinFET Technology Scaling on 3T and 3T1D Cell Performance Under Process and Environmental Variations“
    Z. Jakšić, R. Canal
    3rd Workshop on Workshop on Resilient Architectures, in conjunction with the 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver (Canada), December 2012
  35. “Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm” (Best Paper Award)
    E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
    27th Conference on Design of Circuits and Integrated Systems (DCIS 2012), Avignon (France), November 2012
  36. “Impact of Bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance “
    E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
    11th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2012), Xian (China), October 2012
  37. “Enhancing 3T DRAMs for SRAM replacement under 10nm Tri-Gate SOI FinFETs“
    Z. Jakšić, R. Canal
    30th IEEE International Conference on Computer Design (ICCD’12), Montreal (Quebec), September 2012
  38. “A Novel Variation-Tolerant 4T-DRAM with Enhanced Soft-Error Tolerance“
    S. Ganapathy, R. Canal, D. Alexandrescu, E. Costenaro, A. Gonzalez, A. Rubio
    30th IEEE International Conference on Computer Design (ICCD’12), Montreal (Quebec), September 2012
  39. “Analysis of FinFET Technology on Memories” (invited paper)
    E. Amat,A. Asenov, R. Canal, B. Cheng, J-L. Cruz, Z. Jakšić, M. Miranda, A. Rubio, P. Zuber
    18th IEEE International On-Line Testing Symposium (IOLTS’12), Sitges (Catalonia), June 2012
  40. “Enhancing 6T SRAM Cell Stability by Back Gate Biasing Techniques for 10nm SOI FinFETs under Process and Environmental Variations“
    Z. Jakšić, R. Canal
    19th International Conference on  Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012
  41. “Strain Relevance on the Improvement of the 3T1D Cell Performance“
    E. Amat, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio
    19th International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012
  42. “Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors“
    S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
    29thIEEE International Conference on Computer Design (ICCD’11), Amherst (MA, USA), October 2011
  43. “ New reliability mechanisms in memory design for sub-22nm technologies” (invited paper)
    N. Aymerich, A. Asenov, A. Brown, R. Canal, B. Cheng, J. Figueras, A. Gonzalez, E. Herrero, S. Markov, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, X. Wang, P. Zuber
    17th IEEE International On-Line Testing Symposium (IOLTS’11), Athens (Greece), July 2011
  44. “Impact of Positive Bias Temperature Instability (PBTI) on 3T1D-DRAM Cells“
    N. Aymerich, S. Ganapathy, A.Rubio, R. Canal, A. Gonzalez
    IEEE/ACM Great Lakes Symposium on VLSI, Lausanne (Switzerland), May 2011
  45. “MODEST : A Model for Energy Estimation under Spatio-Temporal Variability“
    S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
    15th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2010) , August 2010 (Austin, Texas)
  46. “Circuit Propagation Delay Estimation Through Multivariate Regression-Based Modeling Under Spatio-Temporal Variability“
    S. Ganapathy, R. Canal, A. Gonzalez, A. Rubio
    IEEE Design, Automation and Test in Europe Conference (DATE’10), March 2010 (Dresden, Germany)
  47. “An hybrid eDRAM/SRAM macrocell to implement first-level data caches “
    A. Valero, J. Sahuquillo, S. Petit, V. Lorente, R. Canal, P. Lopez, J. Duato
    IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 2009 (New York, New Jersey)
  48. “Process Variation Tolerant 3T1D-Based Cache Architectures“
    Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David M. Brooks
    The 40th International Symposium on Microarchitecture (MICRO-40), December 2007 (Chicago, Illinois)
  49. “Process Variation Tolerant Register Files Based on Dynamic Memories“
    Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David M. Brooks
    ASGI’07,Workshop on Architectural Support for Gigascale Integration (In conjunctoin with ISCA 2007), June 2007 (San Diego, California)
  50. “Platform-Agnostic Steal-Time Measurement in a Guest Operating System“
    J. Verdú, J. J. Costa, B. Otero, E. Rodríguez, A. Pajuelo, R. Canal
    ArXiv, abs/1810.01139, pp. 1-4, 2018.
  51. “Power-Efficient Spilling Techniques for Chip Multiprocessors“
    Enric Herrero, José González, Ramon Canal
    International Conference on Parallel and Distributed Computing, (EURO-PAR’10), Ischia (Italy), September 2010
  52. “Elastic Cooperative Caching: An Autonomous Dynamically Adaptive Memory Hierarchy for Chip Multiprocessors “
    Enric Herrero, José González, Ramon Canal
    IEEE 37th International Conference on Computer Architecture (ISCA’10), Saint-Malo (France), June 2010
  53. “Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs“
    Matteo Monchiero, Ramon Canal and  Antonio González
    IEEE 38th International Conference on Parallel Processing (ICPP), Vienna (Austria), September 2009
  54. “Distributed Cooperative Caching“
    Enric Herrero, José González, Ramon Canal
    IEEE/ACM 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), Toronto (CA), Oct.ober 2008
  55. “ Design Space Exploration for Multicore Architectures: A Power/Performance/Thermal View“
    Matteo Monchiero, Ramon Canal and  Antonio González
    The 20th ACM International Conference on Supercomputing (ICS’06), Cairns (Australia)
  56. “ Value Compresson for Efficient Computation ” (slides) Ramon Canal, Antonio González and James E. Smith 2005 European Conference on Parallel Computing (Europar’05), Lisboa (Portugal); Lecture Notes in Computer Science v. 3648, pp. 519-529, August 2005
  57. “ Power- and Performance- Aware Architectures (PhD. dissertation) ” (slides) Ramon Canal (Advisors: Antonio González and James E. Smith) Department of Computer Architecture (UPC-Barcelona) Barcelona (CAT) , June 2004
  58. “ Software- Controlled Operand Gating ” (slides) Ramon Canal, Antonio González and James E. Smith Proc. of the International Symposium on Code Generation and Optimization (CGO-2), Palo Alto (CA-USA), pp. 125-136, March 2004
  59. “Very Low Power Pipelines using Significance Compression” (slides) Ramon Canal, Antonio González and James E. SmithProc. of the International Symposium on Microarchitecture (MICRO-33), Monterey (CA-USA), pp. 181-190, Dec. 2000.
  60. “Toward a European Curriculum for a Master in HPC“
    Dirk Pleiter, Maria-Ribera Sancho, Xavier Martorell, Josep Llosa, Ramon Canal, Eduard Ayguade, Marcin Ostasz; EduHPC-22: Workshop on Education for High Performance Computing (in conjunction with SC’22), Dallas (Texas, USA), November 2022
  61. “Reducing the Complexity of the Issue Logic” (slides) Ramon Canal and Antonio González Proc. of the International Conference on Supercomputing (ICS-01). Sorrento (Italy), June 16-21, 2001
  62. “Dynamic Code Partitioning for Clustered Architectures” Ramon Canal, Joan Manuel Parcerisa and Antonio González International Journal of Parallel Programming vol. 29 n. 1, February 2001, pp. 59-79.
  63. “A Low-Complexity Issue Logic” Ramon Canal and Antonio González Proc. of the International Conference on Supercomputing (ICS-00). Santa Fe (USA). May 8-11, 2000.
  64. “Dynamic Cluster Assigment Mechanisms” Ramon Canal, Joan Manuel Parcerisa and Antonio González Proc. of 6th. Int. Symp. on High-Performance Computer Architecture (HPCA-6), Toulouse (France), Jan. 10-12, 2000 (Best student paper)
  65. “A Cost-Effective Clustered Architecture” Ramon Canal, Joan Manuel Parcerisa and Antonio González Proc. of Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-99), New Port Beach (USA), Oct. 12-16, 1999

Talks

  1. “Vitamin-V: Vitamin-V: pushing for a complete hardware/software RISC-V stack for IoT/Cloud “
    Invited talk FORECAST workshop held with HiPEAC 2023, Toulouse, France, January 2023.
  2. “Deep‐Learning for system security and privacy: the obstacles ahead of us”
    Invited talk at NOPE workshop held with ASPLOS-26, April 2021
  3. “Cross‐Layer Soft‐Error Resilience Analysis of Computing Systems”
    Tutorial at IEEE/IFIP DSN 2020 Conference – June 2020
  4. “Residue checking for Trojan and DFA protection in RSA, SHA and AES cryptographic circuits”
    Invited talk TIMA Lab Grenoble, France, March 2020.
  5. “A Detailed Methodology to Compute Soft Error Rates in Advanced Technologies”
    Invited talk Early System Reliability Analysis for Cross-layer Soft Errors Resilience in Microprocessor Systems Workshop. DATE 2020, February 2020.
  6. “Reliability and Security: two sides of the same coin “
    Invited talk Universitat Rovira i Virgili, Tarragona, Catalonia, November 2018.
  7. “Memory Organization in the Multi/Many-Core Era”
    Invited talk at Intel Microprocessor Technology Lab, Hillsboro (OR-USA), January 2016
  8. “Memory Organization in the Multi/Many-Core Era”
    Invited talk at Intel Microprocessor Research Lab, Bangalore (India), November 2015
  9. “Big Data to wearables, a hardware perspective”, seminar at the Faculty of Pure and Applied Sciences, University of Cyprus, April 2015.
  10. “Cross-layer studies: from technology to circuits and architectures”, Invited talk at the Xi Computer Architecture Research Group, University of Cyprus, April 2015.
  11. “The Uncertainty of Technology and its Consequences”
    Invited talk at the Error-Aware Systems: Opportunities and Challenges for Handling Errors at Multiple Levels track in the  Hipeac Computer Systems Week. Athens (Greece), October 2014
  12. “Reliability in High Performance Computing, pea nuts or hot potato?”  
    Invited talk at the IEEE International On-Line Testing Symposium (IOLTS 2014), Platja d’Aro (Catalonia), July 2014
  13. “FinFETs and their impact on SRAM and DRAM memories”
    Invited talk at the FP7 Variability and Reliability Showcase, held in the ESSCIRC/ESSDERC 2013. Bucharest (Romania), September 2013
  14. “New cells and reliability mechanisms for next generation memories”
    Invited talk at the CASTNESS’13, Computing Architectures Software tools and nano-Technologies. For Numerical Embedded and Scalable Systems. Barcelona (Catalonia), June 2013
  15. “Are FinFETs the panacea?“
    Invited talk at the Workshop The intertwining challenges of reliability, testing and verification. Held in the Hipeac Systems Week 2012. Ghent (Belgium), October 2012
  16. “The memory hierarchy in the many-core era: friend or foe?“
    Keynote at the 1st International Workshop on On-chip Memory Hierarchies and Interconnects (OMHI). Held in conjunction with Europar-2012. Rhodes (Greece), August 2012
  17. “FinFET Technology for Memories: Pros and Cons“
    Invited talk at IEEE International On-Line Testing Symposium (IOLTS 2012), Sitges (Catalonia), June 2012
  18. “Compensation Mechanisms at Digital Circuit Design Level“
    Keynote at the 3rd European Workshop on CMOS Variability (VARI 2012), Nice (France), June 2012
  19. “Challenges in Computing in the Age of Heterogeneous Platforms“
    Panel member at the XXIX IEEE International Conference of Computer Design (ICCD 2011), Amherst (MA, USA), October 2011
  20. “Low Power Microarchitectures, tools for power/reliability simulation/estimation“
    Seminar at École thématique ARCHI’11, Mont-Louis (France), June 2011
  21. “TRAMS: peeking into the future of technology and systems“
    Invited talk at TF on reliability at HiPEAC Spring Computing Systems Week, Chamonix (France), April 2011
  22. “Memory Organization in the Multi/Many-Core Era”
    Invited talk at Intel Microprocessor Technology Lab, Hillsboro (OR-USA), February 2011
  23. “Run-time PVT variations monitoring and adaptation”
    Invited talk at Intel Circuit Research Lab, Hillsboro (OR-USA), February 2011
  24. “Reliability: the next big challenge”
    Invited talk at Universitat Politècnica de València, València (Spain), November 2010
  25. “Future trends and challenges in the microprocessor world”
    Invited talk at Universidad del Turabo, Caguas (Puerto Rico), March 2007
  26. “Future trends and challenges in the microprocessor world”
    Invited talk at Universidad Metropolitana, San Juan (Puerto Rico), March 2007
  27. “Computer architecture research by the Mediterranean”
    Invited talk at Harvard University, Cambridge (MA-USA), October 2006
  28. “How to keep cool and get the job done”
    Invited talk at Northeastern University, Boston (MA-USA), June 2006
  29. “Low Power Pipelines using Significance Compression”
    Invited talk at Penn State University, Pittsburgh (PA-USA), December 2000

Students

PhD Students

Andreu Gironès (MSc)

Manish Rana (PhD’16)

Zoran Jaksic (PhD’15)

Intel Doctoral Student Programme Honoree 2014

Shrikanth Ganapathy (PhD’14)

Intel Doctoral Student Programme Honoree 2012

Enric Herrero (PhD ’11)

UPC Outstanding PhD Award.

Projects

All the projects

https://futur.upc.edu/RamonCanalCorretger

Current Projects

Past Projects